The recent trend in miniaturizing integrated circuits (IC or chip) has lead to various types of IC packages, such as chip scale packages (CSP).
For example, in a wire-bonded CSP, a chip is electrically connected to an underlying substrate by bonding wires. Such a configuration requires a size increase both in height to accommodate wire loops and in width and/or length to accommodate wire bonding pads. To further reduce the package size, flip-chip CSPs have been proposed.
In a flip-chip CSP, a chip is electrically connected to an underlying substrate not by wires but by solder bumps.
In such a flip-chip CSP, if there is a mismatch in the coefficients of thermal expansion (CTE) between the chip and the substrate, for example, if the CTE of the substrate is greater than that of the chip, the substrate contracts at a greater rate than the chip when the temperature is reduced, e.g., after a solder-reflowing process. As a result, warpage occurs to the CSP which, in turn, causes product reliability and/or production yield issues.
To prevent warpage, it has been proposed to add an underfill material between the chip and the substrate to “lock” the chip to the substrate.